Method of and circuit for sampling a frequency difference in an integrated circuit
US7711328B1 · kind B1 · utility
4Cited by
28References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2006 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Jul 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1075
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of sampling a frequency difference in an integrated circuit is disclosed. The method comprises the steps of receiving a clock signal in a first clock domain; comparing a count of the clock signal in the first clock domain to a predetermined value N; converting the result of the comparison to a second clock domain; and generating an error signal representing the difference between the count of the first clock signal and the count of a second clock signal in the second clock domain. A circuit for sampling a frequency difference in an integrated circuit is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.