Patent · US Active

Test circuit arrangement

US7711998B2 · kind B2 · utility

3Cited by

11References

19Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventor

Bernd Foeste · Dresden, DE

Key dates

Filing date	Mar 30, 2007
Grant date	May 4, 2010
Priority date	—
Expiry date	Dec 6, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/41
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A test circuit arrangement for testing latch units is provided which includes a) a voltage generator configured to adjust a voltage potential difference between a first ground line and a second ground line of the latch units and/or to adjust a voltage potential difference between a first supply voltage line and a second supply voltage line of the latch units; b) combiner configured to combine logical outputs of the latch units; and c) determiner configured to determine the voltage potential difference between the first ground line and the second ground line and/or the voltage potential difference between the first supply voltage line and the second supply voltage line in a state when all of the latch units have identical logical outputs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.