Characterization and verification for integrated circuit designs
US7712056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2007 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | May 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/70
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.