Small feature integrated circuit fabrication
US7713824B2 · kind B2 · utility
1Cited by
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12Claims
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Assignee
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Key dates
| Filing date | Feb 21, 2007 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jul 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70466
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for controlling etching during photolithography in the fabrication of an integrated circuit in connection with first and second features that are formed on the integrated circuit having a gap there between comprising depositing a layer of photoresist on the integrated circuit, selectively exposing portions of the photoresist through at least one photolithography mask having a pattern including means for alleviating line end shortening of the first and second lines adjacent the gap, and developing the photoresist after the selective exposing step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.