LDMOS transistor double diffused region formation process
US7713825B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2007 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Nov 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.