Trench isolation structure
US7714325B2 · kind B2 · utility
0Cited by
36References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2007 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jul 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a thermal oxide layer on the surface of a semiconductor substrate exposed during a semiconductor fabricating process. The thermal oxide layer is to be thin to minimize silicon substrate defects caused by volume expansion. A chemical vapor deposition (CVD) layer is then formed on the thin thermal oxide layer, creating a required thickness. The thin thermal oxide layer and the CVD material layer are formed in the same CVD apparatus. As a result, a process can be simplified and a particle-leading pollution can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.