Semiconductor device
US7714357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2008 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Oct 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.