Castellated gate MOSFET device capable of fully-depleted operation

US7714384B2 · kind B2 · utility

Inventor

• John J. Seliskar · Charlottesville, US

Key dates

• Filing date: Apr 27, 2007
• Grant date: May 11, 2010
• Expiry date: Apr 27, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A castellated-gate MOSFET I/O device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, and a channel-forming region is also disposed therein between the source and drain regions. Trench isolation insulator islands, having upper and lower surfaces, surround the source and drain regions as well as the channel-forming region. The channel-forming region includes a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements, and a top gate member interconnects the gate elements at their upper vertical ends to cover the channel elements. The conductive channel elements are super-self-aligned from the gate structure to the source and drain regions. Finally, a dielectric layer separates the conductive channel elements from the gate structure.