Patent · US Active

Retention test system and method for resistively switching memory devices

US7715258B2 · kind B2 · utility

3Cited by

4References

25Claims

0Family size

Assignees

Qimonda AG · DE
Altis Semiconductor · FR

Inventors

Ralf Symanczyk · Bad Aibling, DE
Paul-Henri Albarede · Mennecy, FR

Key dates

Filing date	Dec 21, 2007
Grant date	May 11, 2010
Priority date	—
Expiry date	Dec 21, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG11C2213/79
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a bias voltage to at least one memory cell of the memory device to be tested.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.