Using dedicated read output path to reduce unregistered read access time for a FPGA embedded memory
US7715271B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2008 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Oct 28, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.