Programmable logic device integrated circuit with dynamic phase alignment capabilities
US7715467B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 17, 2006 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Apr 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Adjustable transceiver circuitry is provided for programmable integrated circuits such as programmable logic device integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The dynamic phase alignment circuit contains a bypassable synchronizer. Four modes of operation are supported by the transceiver circuitry including a normal source synchronous mode, a normal dynamic phase alignment mode, a soft clock data recovery mode, and a phase-locked-loop source synchronous mode. In normal source synchronous mode, the dynamic phase alignment circuit performs no phase alignment or clock rate matching. In normal dynamic phase alignment mode, the dynamic phase alignment circuit performs only phase alignment operations. In soft clock data recovery mode, programmable logic on the programmable integrated circuit is configured to perform rate matching and phase alignment. In phase-locked-loop source synchronous mode, phase alignment and board level deskewing operations are performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.