Decision feedback equalizer (DFE) architecture
US7715474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2007 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jan 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03445
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A decision feedback equalizer (DFE) and method includes summer circuits to add a dynamic feedback signal representing an h2 tap to a received input and to speculate on an h1 tap. Data slicers receive and sample the outputs of the summer circuits using a clock signal to produce even data bits and odd data bits. First and second multiplexers receive the even data bits and the odd data bits. A first output latch is configured to receive an output of the first multiplexer to provide a select signal for the second multiplexer and to drive the dynamic feedback signal to an even half summer circuit of the summer circuits. A second output latch is configured to receive an output of the second multiplexer to provide a select signal for the first multiplexer and to drive the dynamic feedback signal to an odd half summer circuit of the summer circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.