Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes
US7716423B2 · kind B2 · utility
2Cited by
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10Claims
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Key dates
| Filing date | Feb 7, 2006 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jun 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled. Further, for some embodiments, LRU bits may be modified to change the way a binary tree structure is traversed to avoid selecting a hint locked entry for replacement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.