Effective use of a BHT in processor having variable length instruction set execution modes
US7716460B2 · kind B2 · utility
48Cited by
1References
16Claims
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Assignee
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Key dates
| Filing date | Sep 29, 2006 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Mar 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.