Dynamic timing adjustment in a circuit device
US7716511B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2006 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Feb 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.