Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays
US7718448B1 · kind B1 · utility
4Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2005 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Mar 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/603
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS transistor arrays are similar to standard LDMOS transistor arrays such that the results of the modified LDMOS transistor arrays can be used to predict the results of the standard LDMOS transistor arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.