Low temperature doped silicon layer formation
US7718518B2 · kind B2 · utility
3Cited by
88References
31Claims
0Family size
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Key dates
| Filing date | Dec 14, 2006 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Jun 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.