Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof

US7719058B2 · kind B2 · utility

Inventor

• John J. Seliskar · Charlottesville, US

Key dates

• Filing date: Oct 12, 2005
• Grant date: May 18, 2010
• Expiry date: Mar 28, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body. The channel-forming region within the isolated castellated-gate MOSFET region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. One or more of the trench isolated regions may contain at least one type or polari…