Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement
US7719062B2 · kind B2 · utility
21Cited by
6References
21Claims
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Key dates
| Filing date | Dec 29, 2006 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Sep 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.