On-chip electromigration monitoring
US7719302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Jun 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318533
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.