Signal receiver circuit capable of improving area and power efficiency in semiconductor integrated circuits
US7719323B2 · kind B2 · utility
3Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Dec 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/062
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.