Method of programming cells of a NAND memory device
US7719894B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jul 26, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Jun 16, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.