Semiconductor device
US7719906B2 · kind B2 · utility
6Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2008 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Nov 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area is tested, a refresh counter circuit for generating and outputting refresh addresses rearranges the address in such a manner that a row address of the redundancy area is substantially reduced and placed on a lower-order bit side inclusive of the LSB of the counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.