Method and apparatus for redirection of machine check interrupts in multithreaded systems
US7721148B2 · kind B2 · utility
10Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Mar 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.