Designated MOSFET and driver design to achieve lowest parasitics in discrete circuits
US7721232B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 29, 2004 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Feb 5, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Apparatus are described for a pair of MOSFET power transistors, a MOSFET driver, and an idealized circuit layout utilized in a power stage such as that of a power conversion system. The power stage comprises a pair of MOSFET transistors having substantially identical electrical characteristics and complementary package configurations for simplifying and optimizing the layout of the power stage on a single side or layer of a printed circuit board. The ideal layout effectively avoids parasitic circuit components, minimizes layout area and costs, and permits operation at higher switching frequencies. A new MOSFET transistor pin configuration is also described that is essentially a functional mirror or functional complement of an existing MOSFET transistor pin configuration to provide the complementary package configurations and the optimized PCB layout. A customized MOSFET driver pin configuration further optimizes the power stage layout by arranging the pins of the driver to coordinate with those of the MOSFET transistor pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.