Method and system for implementing edge optimization on an integrated circuit design
US7721235B1 · kind B1 · utility
8Cited by
11References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Nov 16, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method, system, and computer program product for performing edge optimization on an electronic design. According to some approaches, the number of edges and/or the length of edges within an IC design are configured for optimized manufacturability and yield of an integrated circuit. The edge optimization may occur in real-time during layout, placement, and/or routing, or occur in a post-optimization step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.