Low temperature polysilicon oxide process for high-K dielectric/metal gate stack
US7723173B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2009 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Mar 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum nitride and polysilicon layers. A thin polysilicon layer deposited over the stacks is converted to an oxide using a low temperature ultraviolet ozone oxidation process or a plasma nitridation using decoupled plasma nitridation or NH3 annealing. The oxide provides a coating over the top and sides of the stacks to protect metal and interfaces from oxidation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.