Ajith Varghese
15Patents
3h-index
21Co-inventors
56Inventor score
Filing activity: Oct 14, 2003 → Aug 5, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7838370B2 | Highly selective liners for semiconductor fabrication | Electricity | 42 | Active |
| US7396728B2 | Methods of improving drive currents by employing strain inducing STI liners | Electricity | 15 | Active |
| US8119470B2 | Mitigation of gate to contact capacitance in CMOS flow | Emerging Cross-Sectional Technologies | 6 | Active |
| US7384861B2 | Strain modulation employing process techniques for CMOS technologies | Electricity | 3 | Expired |
| US7227201B2 | CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers | Electricity | 3 | Expired |
| US7435651B2 | Method to obtain uniform nitrogen profile in gate dielectrics | Emerging Cross-Sectional Technologies | 3 | Active |
| US7696021B2 | Semiconductor device manufactured using a non-contact implant metrology | Electricity | 1 | Active |
| US6924239B2 | Method for removal of hydrocarbon contamination on gate oxide prior to non-thermal nitridation using “spike” radical oxidation | Electricity | 1 | Expired |
| US7682988B2 | Thermal treatment of nitrided oxide to improve negative bias thermal instability | Electricity | 1 | Expired |
| US7723173B2 | Low temperature polysilicon oxide process for high-K dielectric/metal gate stack | Electricity | 1 | Active |
| US7514308B2 | CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers | Electricity | 1 | Active |
| US7855111B2 | Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates | Electricity | 0 | Active |
| US8828855B2 | Transistor performance using a two-step damage anneal | Electricity | 0 | Active |
| US9054056B2 | Transistor performance using a two-step damage anneal | Electricity | 0 | Active |
| US9029251B2 | Transistor performance using a two-step damage anneal | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.