Methods and articles incorporating local stress for performance improvement of strained semiconductor devices
US7723720B2 · kind B2 · utility
2Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2005 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Nov 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device (450) includes a semiconductor chip (400) having at least one selectively thinned substrate (cavity) region (410). A package (460) is provided for mounting, enclosing and electrically connecting the chip (400) to the outside world, and structure for applying external stress (470) to induce strain in the thinned substrate region (410). The external stress is preferably adjustable, such as by varying the gas flow (or a vacuum) applied through a pressure valve.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.