Semiconductor device with its test time reduced and a test method therefor
US7724024B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Jun 26, 2009 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jun 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318385
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.