Reducing power consumption in an amplification stage driving a sample and hold circuit while maintaining linearity
US7724042B2 · kind B2 · utility
5Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Aug 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input signal to be sampled by a sample and hold circuit is amplified separately by two amplifiers. The output of the first amplifier is provided to a boost circuit to maintain the impedance of a sampling switch contained in a signal dependent boost switch substantially constant. The output of the second amplifier is sampled via the sampling switch, and the sample is stored in a storage element. The second amplifier drives a reduced load, and may be implemented as a low bandwidth, low power amplifier to reduce overall power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.