Patent · US Active

Memory arrangement having efficient arrangement of devices

US7725647B2 · kind B2 · utility

0Cited by

3References

23Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Paul Wallner · Prien am Chiemsee, DE
Tim Schoenauer · Peising, DE
Peter Gregorius · Munich, DE
Daniel Kehrer · Eferding, AT

Key dates

Filing date	Feb 27, 2007
Grant date	May 25, 2010
Priority date	—
Expiry date	Sep 1, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0607
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.