Peter Gregorius
68Patents
13h-index
59Co-inventors
79Inventor score
Filing activity: Mar 4, 2002 → Feb 23, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7414917B2 | Re-driving CAwD and rD signal lines | Electricity | 69 | Expired |
| US6700361B2 | Voltage regulator with a stabilization circuit for guaranteeing stabile operation | Physics | 40 | Expired |
| US7173993B2 | Method for sampling phase control | Electricity | 39 | Expired |
| US7282999B2 | Method and device for generating a clock signal using a phase difference signal and a feedback signal | Electricity | 34 | Expired |
| US7339840B2 | Memory system and method of accessing memory chips of a memory system | Physics | 23 | Expired |
| US8031539B2 | Memory device and memory system comprising a memory device and a memory control device | Physics | 20 | Active |
| US7292662B2 | Feed forward clock and data recovery unit | Electricity | 18 | Expired |
| US8015438B2 | Memory circuit | Physics | 16 | Active |
| US8120958B2 | Multi-die memory, apparatus and multi-die memory stack | Physics | 15 | Active |
| US7095803B2 | Method of reconstructing data transmitted over a transmission path in a receiver and corresponding device | Electricity | 15 | Expired |
| US7404050B2 | Method of operating a memory device, memory module, and a memory device comprising the memory module | Physics | 15 | Expired |
| US7221615B2 | Semiconductor memory chip | Physics | 13 | Expired |
| US7184360B2 | High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips | Physics | 13 | Expired |
| US7334150B2 | Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals | Physics | 13 | Expired |
| US7475187B2 | High-speed interface circuit for semiconductor memory chips and memory system including the same | Physics | 11 | Active |
| US7457391B2 | Clock and data recovery unit | Electricity | 10 | Active |
| US8041865B2 | Bus termination system and method | Physics | 10 | Active |
| US8914589B2 | Multi-port DRAM architecture for accessing different memory partitions | Emerging Cross-Sectional Technologies | 9 | Active |
| US7848153B2 | High speed memory architecture | Electricity | 8 | Active |
| US7292631B2 | Feed forward equalizer and a method for analog equalization of a data signal | Electricity | 8 | Expired |
| US7928525B2 | Integrated circuit with wireless connection | Electricity | 7 | Active |
| US7088976B2 | Device for reconstructing data from a received data signal and corresponding transceiver | Electricity | 6 | Expired |
| US8305834B2 | Semiconductor memory with memory cell portions having different access speeds | Physics | 6 | Active |
| US8108643B2 | Semiconductor memory chip and memory system | Physics | 5 | Active |
| US7325152B2 | Synchronous signal generator | Physics | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.