Feature failure correlation
US7725849B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2005 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Oct 3, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for determining the likelihood that a known feature in an integrated circuit design will cause a defect during the manufacturing process. According to some of these techniques, various logical units that incorporate an identified design feature are identified, and the amount that the design feature occurs in each of a plurality of these logical units is determined. The failure rate of integrated circuit portions corresponding to at least these logical units are then obtained. A feature failure coefficient indicating the likelihood that the feature will cause a defect then is determined by correlating the failure rates with the amount of occurrences of the feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.