Contact configuration and method in dual-stress liner semiconductor device
US7727834B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 2008 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jun 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device may comprise forming a conductive layer on a substrate, removing at least one portion of the conductive layer to form a plurality of separate conductive lines, forming a first stress-inducing layer of a first stress type on the conductive lines and the substrate, and removing a portion of the first stress-inducing layer such that a remaining portion of the first stress-inducing layer is disposed on a first subset of the conductive lines but not a second subset of the conductive lines and has a boundary disposed between two of the conductive lines. This method, along with other methods and various semiconductor devices, are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.