Method of producing an integrated circuit having a capacitor with a supporting layer
US7727837B2 · kind B2 · utility
15Cited by
4References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2007 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jan 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.