Method of manufacturing semiconductor device with dual gates
US7727841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2006 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Aug 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.