Ultra shallow junction formation by solid phase diffusion
US7727845B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2005 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | May 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.