Method of manufacturing a wafer level package that uses the same seed layer for selectively electroplating a rewiring pattern and a conductive pillar
US7727877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2008 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jun 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.