Method for improved power distribution in a three dimensional vertical integrated circuit
US7727887B2 · kind B2 · utility
10Cited by
16References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | May 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.