Method of forming embrittled areas inside wafer for division
US7728257B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 24, 2007 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Sep 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67092
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming embrittled areas in multiple layers inside a wafer so as to enable the wafer to be divided correctly even at areas where embrittled areas intersect. In a first direction embrittling step an embrittled area is formed as a bottom layer, in a second direction embrittling step embrittled areas are formed as a bottom layer and a second layer, in the first direction embrittling step the embrittled areas are formed as a second layer and a third layer, and thereafter, the second direction embrittling step and the first direction embrittling step are alternately implemented, and finally, in the second direction embrittling step, embrittled area is formed as a top layer, so that a length of an unprocessed area is contained within a range that does not interfere with division.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.