Semiconductor device, wiring substrate, and method for manufacturing wiring substrate
US7728439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2003 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Aug 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer (5) is provided on one surface of a silicon base (3). An electrode as the uppermost layer of the wiring layer (5) is provided with an external bonding bump (7). A through-electrode (4) is formed in the base (3) for electrically connecting the wiring layer (5) and an electrode terminal. The electrode terminal on the chip mounting surface is bonded to an electrode terminal of a semiconductor chip (1) by an internal bonding bump (6). The thermal expansion coefficient of the silicon base (3) is equivalent to that of the semiconductor chip (1) and not more than that of the wiring layer (5).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.