System including a buffered memory module
US7729151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2006 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Mar 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a master device and a first memory module having a plurality of integrated circuit memory devices and a plurality of integrated circuit buffer devices that operate in first and second modes of operation (bypass mode). In a first mode of operation, a first memory module provides read data from the plurality of integrated circuit memory devices (via a integrated circuit buffer device) on a first signal path to the master and a second memory module simultaneously provides read data from its plurality of integrated circuit memory devices (via another integrated circuit buffer device on the second module) on a third signal path coupled to the master device. In a second mode of operation, the first memory module provides first read data from its plurality of integrated circuit memory devices (via the integrated circuit buffer device) on the first signal path and second read data from its plurality of integrated circuit memory devices (via the integrated circuit buffer device) on a second signal path that is coupled to a second memory module. An integrated circuit buffer device in the second memory module then bypasses the second read data from the second signal path and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.