Pipelined packet switching and queuing architecture
US7729351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2006 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Aug 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/506
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets. These features can include a recycle path coupling a gather stage circuit and a fetch stage circuit and can include sequence number logic configured to associate sequence numbers with multicast packet headers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.