Translation of commands in an interconnection of an embedded processor block core in an integrated circuit
US7730244B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2008 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jul 31, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.