Adaptively reducing memory latency in a system
US7730264B1 · kind B1 · utility
6Cited by
3References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2006 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Mar 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for routing an early request for requested data on a bypass path around a transaction processing path of a first agent if the requested data is not present in a cache memory of the first agent, and opportunistically transmitting the early request from the first agent to a second agent based on load conditions of an interconnect between the first agent and the second agent. In this way, reduced memory latencies may be realized. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.