System and method for saving and restoring a processor state without executing any instructions from a first instruction set
US7730330B1 · kind B1 · utility
12Cited by
297References
157Claims
0Family size
Inventors
Key dates
| Filing date | Aug 10, 2005 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.