Integrated memory system
US7730357B2 · kind B2 · utility
9Cited by
5References
18Claims
0Family size
Inventors
Key dates
| Filing date | Mar 19, 2004 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | May 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.