Method of forming a MOS device with an additional layer
US7732289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2005 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.