Post last wiring level inductor using patterned plate process
US7732295B2 · kind B2 · utility
0Cited by
21References
6Claims
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Assignee
Inventors
Key dates
| Filing date | Jul 10, 2008 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Jul 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.